The present invention generally relates to the testing of semiconductor chips and wafers and, more particularly, to a method and device for testing a chip or wafer without damaging contact points on the chip or wafer while providing a reliable electrical conductive path from each contact point on the chin or wafer to a corresponding point on a testing substrate.
Most modern electronic systems include one or more integrated circuit (IC) chips bonded to a suitable substrate which, in turn, is connected to an electronic package such as a module, card, board, or gate. There are a variety of known techniques for connecting the chips to a substrate such as a circuit board. An overview of some of these techniques follows.
FIG. 1 shows one prior art technique for attaching an IC package 100 to a circuit board 105. In this particular case, the IC 110 itself is inside a plastic, dual, in-line package 100 having bent metal leads 115. (For convenience, an individual IC 110 is often referred to as a xe2x80x9cdie.xe2x80x9d) Wire leads 120 are used to connect the IC 110 to the bent leads 115 of the package 100. To mount the package 100, the leads 115 are inserted into matching holes 125 in the circuit board 105 and fixed in place by solder.
FIG. 2 shows another prior art technique of attaching an IC to a circuit board generally known as the xe2x80x9csolder-bumpxe2x80x9d approach. In this technique, the die 110 has metal pads on which small bumps of solder 130 are deposited. The die 110 is aligned over matching metal pads 135 on the circuit board 105. When the assembly is heated to above the melting point of solder 130, the solder melts to form an electrical contact between the IC 110 and the circuit board 105. In this configuration, the die 110 is upside down from what is shown in FIG. 1. Thus, the configuration is also known as a xe2x80x9cflip-chip.xe2x80x9d
Closely related to die connection technology is the increasing use of multi-chip module (MCM) design and packaging. In short, MCM techniques seek to combine a number of different dies on a common substrate. Benefits of MCM systems include increased operating clock speeds and reduced product footprint. Some in the semiconductor industry predict that as xe2x80x9creal estatexe2x80x9d (i.e., surface area) on IC devices continues to shrink, flip-chip bonding techniques will become dominant. Some of the benefits of the flip-chip bonding technique over wire bonding or tape automated bonding techniquesxe2x80x94two other common die connection methodsxe2x80x94are summarized in Table 1. Tape automated bonding is presently a preferred method of bonding dies to MCM-like substrates.
As shown in Table 1, the flip-chip technique requires less bonding area (for a given size die, e.g., 400 mils on a side) than do either wire or tape automated bonding methods. This advantage allows, in turn, for an increased packing density of dies on an MCM substrate. Flip-chip bonding also provides lower levels of resistance, capacitance, and inductance per contact than do the other methods. All of these features support increased operational speeds.
A significant problem in assembling MCM systems, or other multi-die circuits, is that dies purchased from silicon foundries usually cannot be assumed to be 100% xe2x80x9cgoodxe2x80x9d (i.e., functional). In a large multi-die circuit, the probability that a completed circuit will contain all good dies decreases exponentially as the number of dies increases. A significant problem for companies that assemble dies into circuits, e.g., system houses, is that of testing purchased dies to ensure that they are in fact good.
From the point of view of the system house, the problem is being able to obtain dies that are xe2x80x9cknown goodxe2x80x9d so that the system house does not have to incur the cost of testing each purchased die. On the other hand, silicon foundries make their money in running wafers and often do not want to perform costly functional testing. (A plurality of chips or dies are formed on a single wafer, during semiconductor manufacturing, which is then diced.) Many silicon foundries might be willing to perform, at most, a worst-case DC test at the wafer level.
If a system house avoids testing in manufacturing a one-hundred die MCM, for example, and any one or more of the dies are bad, the system house incurs the added costs of fault isolation and die removal and replacementxe2x80x94a possibly time-consuming and costly endeavor. Because of the costs of these operations, all of the forward-thinking semiconductor companies are now developing capabilities to perform bare die testing in preparation for flip-chip applications.
In semiconductor manufacturing, after a plurality of chips are formed on a wafer, each of the chips are commonly probed in sequence to initially check certain of their electrical characteristics. Following this initial probing, the wafer is diced, then packaged and subjected to a burn-in acceleration test to remove those products subject to initial failure. This acceleration test simulates long-time performance by operating a circuit at an elevated temperature (typically about 150xc2x0 C.) while selected signal patterns and sequences are applied to the circuit. As MCM designs become more prevalent, new ways to conduct burn-in tests become more urgent, especially because replacement of faulty chips in an MCM is difficult to automate and a reworked MCM is typically not as reliable as an MCM which was not reworked. Disposal of an MCM having a single faulty chip is costly and, therefore, is not a desirable solution.
The processes of mounting individual dies to substrates or sequentially testing individual chips before they are diced are time consuming and costly alternatives. A considerable amount of time can be saved by testing an entire wafer at once. Accordingly, such all-encompassing tests are desirable.
These tests usually incorporate a test probe. One type of conventional test probe has a plurality of fixed needles mounted on respective cantilevered tungsten wires supported on an epoxy substrate. The wires are connected to an external tester and the needles are brought into contact with respective ones of the chip input/output (I/O) pads. Thus, the needles serve as contact electrodes. This needle and cantilevered wire arrangement, although used for many years in the semiconductor industry, is not suitable for high-density products. It has also been found that, when the chip under test is heated during burn-in testing, thermal expansion differences between the needles, the cantilevered wires, and the chip prompt the needles to shift from their original position. This thermal shifting is especially exaggerated when the chips are being tested in wafer (i.e., un-diced) form and can cause false readings or inputs. Thus, this probe technology is ill-adapted for reliable burn-in testing before dicing.
One attempt to meet the new requirements of testing MCM technology was disclosed by U.S. Pat. No. 5,625,298 issued to Hirano et al. (discussing T. Tada et al., xe2x80x9cA Fine Pitch Probe Technology,xe2x80x9d 1990 International Test Conference, pages 900-06). In this attempt, probe contact electrodes were formed on the surface of a glass board by a lithographic technique. Each contact was electrically connected to an external tester via a respective conductive via passing through a hole on the board. The metal contact electrodes are stiff, however, and do not allow for significantxe2x80x94although smallxe2x80x94variations in the co-planarity of the wafer contacts. Consequently, the metal contact electrodes cannot compensate for small variations in the thickness of wafer metallizations or substrate pads, or perturbations in the surface of a wafer or substrate, not to mention solder bumps. Moreover, the process to manufacture was found to be complicated and costly.
One prior attempt to resolve this compensation problem is disclosed By E. Klink et al. in xe2x80x9cHigh-Performance Test System,xe2x80x9d IBM Technical Disclosure Bulletin, Vol. 33, No. 1A, pages 124-25 (Jun. 1990). The article teaches applying lead-tin C4 (Controlled Collapse Chip Connection) solder bumps to the wafer pads and forming conductive copper dendrites on corresponding pads formed on a silicon carrier. The two silicon parts have substantially flat surfaces. Consequently, all chip positions can be contacted in parallel and, compared with standard needle contacts, only a minimum of compressive force is required.
Commonly assigned U.S. Pat. No. 5,420,520, issued to Anschel et al., teaches a method of testing chips using a conductive dendrite contact. FIG. 3 (which corresponds to FIG. 4 of the patent) shows a cross-sectional schematic representation of a burn-in board 140 having dendritic contacts 138 aligned with C4 bumps 142 formed on a chip 110. A problem with this method is that the conductive dendrite contacts 138 leave indentations in the C4 s after their removal, and the C4 bumps 142 have to be reflowed following the testing procedure. The added expense and time required to reflow the C4 bumps 142 are undesirable; the present invention renders this step unnecessary.
In an effort co reliably test integrated circuit chips and at the same time prepare them for assembly in an MCM, U.S. Pat. No. 5,440,239 issued to Zappella et al. discloses a method of forming a Transferable Solder Bump (TSB) on a test substrate. As shown in FIG. 4, which corresponds to FIG. 3 of the patent, die 110 has an aluminum pad 150 through which electrical connections can be made. The test board or substrate 160 includes an electrical-contact pad, such as an aluminum pad 170, and a TSB stack 180. The TSB stack 180 is made up of a number of metallization layers: a vapor-deposited protected conductor layer 182 comprised of chromium; a solder bump 184 comprised of tin, lead-tin, an indium solder alloy, or various other alloys depending on the target melting point; a diffusion layer 186 comprised of copper or a nickel-copper alloy; and a top layer 188 of gold that eventually forms a permanent contact with the aluminum pad 150 of the die 110.
The test device 190 is bonded to the die 110 through thermal compression or thermalsonic techniques. As the name implies, thermal compression bonding uses compression and heat to form a bond between the gold layer 188 and the aluminum pad 150 of the die 110. Thermalsonic bonding techniques use compression, heat, and ultrasonic energy to introduce a scrubbing action between the gold layer 188 and the aluminum pad 150 of the die 110. Once bonded, the test device 190 is plugged into a test jig for testing. If the die 110 proves to be reliable, the die 110 is removed from the substrate 160, with gold layer 188, diffusion layer 186, and solder bump 184 intact, by elevating the air temperature and allowing the chromium layer 182 to oxidize. Thus, the tested die 110 is provided with solder bumps 184 and is ready for incorporation into an MCM or other package.
A problem with this method is that the pads, solder bumps, and associated metallic layers do not provide a sufficient margin of error along the Z-axis for testing an entire wafer. Furthermore, the method requires many steps, including the costly step of vapor deposition of the chromium layer 182. In addition, xe2x80x9cbadxe2x80x9d dies 110 are discarded along with the testing module and substrate, which entails a further expense in lost materials.
U.S. Pat. No. 5,611,884, issued to Bearinger et al., discloses an Electrically Conductive Adhesive (ECA) material containing silicone resin, siloxane gum, and a conductive particulate material. The composite exhibits properties of electrical conductivity and a tacky surface. FIGS. 3A-3C of this patent show a method of attaching and detaching a chip having C4 bumps formed on its contacts to and from a substrate using the ECA material. The conductive particulate material of the ECA material may be spherical gold particles spherical, hollow glass microspheres coated with silver, gold, nickel, or copper; or spherical particles of metal alloys such as tin-copper, lead-tin, and gold-tin.
The conductive particulate materials disclosed by Bearinger et al. have several disadvantages, including the spherical shape of the conductive particulates, the relatively high cost of some of the materials (e.g., gold), and the relatively strong adhesion provided by some of the materials (e.g., lead-tin solder). Alternative shapes such as flakes, rather than spheres, might be advantageous in certain applications. Cost savings are always desired. Weaker adhesion would allow cleaner separation between the ECA material and the substrate and, at least in some applications, would be preferred. It would also be advantageous to increase the surface area of contact between the ECA material and the substrate to which it is attached (e.g., by using dendrites) and to increase the conductivity of the ECA material.
The known art has failed to provide a mechanism for rapid, reproducible, low cost, high throughput testing of integrated circuit chips. To overcome the shortcomings of the conventional mechanisms, a new method and device are provided. An object of the present invention is to provide a method and device for testing a chip or wafer having a two-dimensional array of electrical contacts by providing temporary attachment to a substrate having corresponding contacts without unduly increasing the number of steps required to prepare the chip for attaching it to its final assembly. It is further an object of the present invention to provide a method and device for reliably testing and/or burning-in an array of chips in a wafer by providing a reliable, simultaneous electrical connection between each electrical contact on the wafer and a corresponding electrical contact on a test substrate. Still another object of the present invention is to provide a method and device that allow easy chip positioning and temporary attachment and easy removal of chips after testing. A related object is to fill the need for an efficient testing mechanism which can easily and readily feed an MCM-like manufacturing process.
To achieve these and other objects, and in view of its purposes, the present invention provides a method and device for testing a chip or wafer without damaging contact points on the chip or wafer while providing a reliable electrical conductive path from each contact point on the chip or wafer to a corresponding point on a testing substrate. A first embodiment of the method of the present invention, which tests a semiconductor chip using a separable connection, includes the steps of: (1) providing a semiconductor chip having contact pads located in an arrangement on a surface of the semiconductor chip, (2) dispensing and curing an electrically conductive adhesive (ECA) material on the contact pads, (3) providing a test substrate having conductive test pads located on a surface of the test substrate in a mirror image pattern corresponding to the arrangement of the contact pads, (4) optionally forming conductive dendrites or gold-plated copper pads on the test pads, (5) aligning the wafer with the test substrate, (6) moving the wafer and the test substrate together and applying a predetermined force causing the ECA material to conform to the variance in the wafer pads, (7) testing the wafer, (8) removing the force and separating the ECA material from the test pads, (9) applying a solvent to dissolve the ECA material from the contact pads of the wafer, and (10) applying ECA material again or adding solder to the wafer.
A second embodiment of the invention includes the method steps of (1) flowing C4s onto wafer pads, (2) depositing ECA material onto the substrate pads, (3) moving the wafer and the substrate together and applying a predetermined force so that the ECA material conforms to the C4 bumps, (4) testing the wafer, and (5) washing the ECA material off the substrate, thereby readying the C4s for attachment into a final assembly.
A third embodiment of the method of the present invention includes the steps of (1) flowing C4s onto wafer pads; (2) positioning a non-conductive interposer between the wafer and the substrate so that vias in the interposer are aligned with the contacts on the wafer and substrate, the vias being filled with ECA material; (3) moving the wafer and the substrate together and applying a predetermined force so that the ECA material conforms to the C4 bumps and pads of the substrate; (4) testing the wafer; and (5) removing the interposer, thereby readying the C4s for attachment into a final assembly.
A fourth embodiment of the method of the present invention includes the steps of (1) providing a lead base on the wafer at each contact point; (2) applying a gold-tin cap, e.g., through a sputtering process, to each lead base; and (3) then adhering an ECA bump to each gold-tin cap. The wafer and substrate are then (4) aligned and forced together with a predetermined pressure. After the wafer is tested, the ECA bump then (5) is removed and the contacts are prepared for final assembly. A modification of this embodiment replaces the lead base with standard C4 solder bumps and ECA material is adhered to the C4s. The wafer and substrate are aligned, then forced together with a predetermined force and tested.
Another method of testing wafers is contemplated in which a finished wafer with aluminum wire bond pads is treated with zincate, nickel, and gold to prepare the metal surface for bonding to a thermoplastic, electrically conductive adhesive and to provide an excellent electrical interface. The ECA is applied, for example, using a photobumping process. The resulting ECA bumps are plasma-etched to roughen the surfaces of the bumps, to create a high surface area contact, and to expose some of the conductive particles by etching away some of the polymer matrix. Palladium is then plated on the roughened surface of the ECA. The wafer is then brought into contact with plated palladium pads on a glass ceramic carrier surface acting as the test probes and dendritic palladium contacts are formed between the palladium probes and the ECA bumps on the wafer pads. After the electrical connection is made, the wafer is tested and known good die are identified. On completion of the testing, the ECA bumps are stripped by wet processing with a solvent such as ethyl benzoate, leaving a gold surface exposed. After dicing, the dies identified as good may be bonded into packages using gold wire.
The above method can be modified by applying the ECA bumps to the test probe fixture instead of to the wafer. In this case, the probe pads are bumped with ECA material which is then plasma etched and plated with palladium. The probe and wafer are then brought together for testing. The resulting structure provides a test probe interface which is mechanically compliant to accommodate tolerances of the probe carrier, ECA bump heights, and wafer contact tolerances and which is capable of forming a high-quality electrical interconnection due to the palladium dendrite growth from the ECA bump surface into the target wafer contact surface.
The above method can be further modified for use with C4 bump wafer processing as follows. After the ball limiting metallurgy (BLM) is deposited on the wafer pads, ECA bumps are formed in place of the C4s. The bumps are plasma etched to roughen the surface and expose the conductive particles. Palladium is then plated on the ECA bump. A test probe having palladium pads on a carrier (formed of glass ceramic, silicon quartz ceramic, or similar material) is brought into contact with the plated ECA bumps on the wafer. Palladium dendrites are formed between the contacts to enhance the electrical contact of the test probe to the compliant conductive bumps. After testing, the die can be diced and assembled to circuit packages using the ECA flip chip attach assembly process or to a chip carrier or board is assembly. Alternatively, the ECA bumps can be stripped using a wet process solvent such as ethyl benzoate after which the wafer can be bumped using standard bump metallurgy, diced, and picked yielding the good die and assembled using an appropriate C4 circuit package.
Standard wafers bumped with 97-3 lead-tin can be tested with this approach as well. The mating ECA-bumped test probe-carrier pads are brought into intimate contact with the solder-bumped wafer. Dendritic palladium contacts are formed between the palladium-plated ECA bumps of the test probes and the solder bumps on the wafer, allowing a continuous electrical path to form. The fixturing pressure at the contact is such that the resiliency of the ECA material is retained and the solder bump on the wafer is not mechanically damaged. When testing is complete, the interface can be easily separated and the test probes can be reused. The C4 wafer may be cleaned if desired and the wafer can proceed to normal subsequent processing such as dice, pick, and assembly.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.